Demonstration of fine pitch FCOB (Flip Chip on Board) assembly based on solder bumps at Fermilab

Bump bonding is a superior assembly alternative compared to conventional wire bond techniques. It offers a highly reliable connection with greatly reduced parasitic properties. The Flip Chip on Board (FCOB) procedure is an especially attractive packaging method for applications requiring a large number of connections at moderate pitch. This paper reports on the successful demonstration of FCOB assembly based on solder bumps down to 250um pitch using a SUESS MA8 flip chip bonder at Fermilab. The assembly procedure will be described, microscopic cross sections of the connections are shown, and first measurements on the contact resistance are presented.Comment: 4 pages, 8 figure

Development of 3D integrated circuits for HEP

Three dimensional integrated circuits are well suited to improving circuit bandwidth and increasing effective circuit density. Recent advances in industry have made 3D integrated circuits an option for HEP. The 3D technology is discussed in this paper and several examples are shown. Design of a 3D demonstrator chip for the ILC is presented

Radiation measurements inside the CDF detector

During the last CDF experimental period from 6/88 to 6/1/89, radiation measurements were made inside the detector on or near the beampipe using various types of monitors. The purpose of the tests was to help predict the radiation levels for future electronics which must be located close to the interaction area. The results from two different types of monitors, PIN diodes and TLD's are reported in this paper. The TLD's (Harshaw/Filtrol type 700) are sensitive to x-rays, gammas, alphas, electrons, and protons. They are calibrated against a cesium source and corrected for nonlinear effects at higher radiation levels. The PIN diodes (Harshaw/Filtrol type DN-156) are sensitive only to neutrons. The devices are calibrated for 1 MeV neutrons and require correction factors for neutrons at other energy levels. All of the monitors were placed just outside of the VTPC, but still inside the CDF magnetic field. The monitors were located 68 inches from the center of the interaction region. The beam pipe is 2 inches in diameter. Therefore the closest monitoring points were on the beampipe or 1 inch from the beam. 5 figs., 2 tabs

A programmable, low noise, multichannel asic for readout of pixelated amorphous silicon arrays

Pixelated amorphous silicon arrays used for detecting X-rays have a number of special requirements for the readout electronics. Because the pixel detector is a high density array, custom integrated circuits are very desirable for reading out the column signals and addressing the rows of pixels to be read out. In practice, separate chips are used for readout and addressing. This paper discusses a custom integrated circuit for processing the analog column signals. The chip has 32 channels of low noise integrators followed by sample and hold circuits which perform a correlated double sample. The chip has several programmable features including gain, bandwidth, and readout configuration

Performance of the CAMEX64 silicon strip readout chip

The CAMEX64 is a 64 channel full custom CMOS chip designed specifically for the readout of silicon strip detectors. CAMEX which stands for CMOS Multichannel Analog MultiplEXer for Silicon Strip Detectors was designed by members of the Franhofer Institute for Microelectronic Circuits and Systems and the Max Planck Institute for Physics and Astrophysics. Each CAMEX channel has a switched capacitor charge sensitive amplifier with 4 sampling capacitors and a multiplexing scheme for reading out each of the channels on an analog bus. The device uses multiple sampling capacitors to filter and reduce input noise. Filtering is controlled through sampling techniques using external clocks. The device operates in a double correlated sampling mode and therefore cannot separate detector leakage current from a charge input. Normal operation of this device is similar to all other silicon readout chips designed and built thus far in that there is a data acquisition cycle during which charge is simultaneously accepted on all channels for a short period of time from a detector array, followed by a readout cycle where that charge or hit information is read out. This device works especially well for colliding beam experiments where the time of charge arrival is accurately known. However it can be used in fixed target or asynchronous mode where the time of charge arrival is not well known. In the asynchronous mode it appears that gain is somewhat dependent on the time interval required to decide whether or not to accept charge input information and thus the maximum signal to noise performance found with the synchronous mode may not be achieved in the asynchronous mode. 18 figs., 5 tabs

Monolithic Active Pixel Matrix with Binary Counters in an SOI Process

The design of a Prototype monolithic active pixel matrix, designed in a 0.15 {micro}m CMOS SOI Process, is presented. The process allowed connection between the electronics and the silicon volume under the layer of buried oxide (BOX). The small size vias traversing through the BOX and implantation of small p-type islands in the n-type bulk result in a monolithic imager. During the acquisition time, all pixels register individual radiation events incrementing the counters. The counting rate is up to 1 MHz per pixel. The contents of counters are shifted out during the readout phase. The designed prototype is an array of 64 x 64 pixels and the pixel size is 26 x 26 {micro}m{sup 2}

Single Event Effects in the Pixel readout chip for BTeV

In future experiments the readout electronics for pixel detectors is required to be resistant to a very high radiation level. In this paper we report on irradiation tests performed on several preFPIX2 prototype pixel readout chips for the BTeV experiment exposed to a 200 MeV proton beam. The prototype chips have been implemented in commercial 0.25 um CMOS processes following radiation tolerant design rules. The results show that this ASIC design tolerates a large total radiation dose, and that radiation induced Single Event Effects occur at a manageable level.Comment: 15 pages, 6 Postscript figure